The present invention generally relates to pattern data processing methods, and more particularly to a pattern data processing method for executing a resizing process on hierarchical pattern data.
Recently, with the increase of the scale and integration density of large scale integrated circuits (LSIs), the required exposure data quantity and the processing time of the pattern processing are increasing considerably, thereby increasing the development cost of the LSIs. The conventional method of executing the pattern processing after the developing processing can no longer cope with the increased number of patterns to the processed. For example, when the conventional method is used to process the pattern data of a 4 Mbit memory, approximately 80,000,000 pattern data must be stored in 30 reels of magnetic tapes. In addition, the processing time required to process such a large data quantity on a computer is extremely long.
Especially in the case of a memory or the like, cells are often repeatedly arranged in an array. The hierarchical pattern processing can effectively utilize the data structure of such a repetition of cells by assigning the hierarchical structure to the exposure data itself and executing the pattern processing in levels of the hierarchical structure. By employing the hierarchical pattern processing, the data processing time can be greatly reduced and the data processing quantity can be compressed considerably in the case of the memory or the like having the repetition of cells. The number of patterns of the LSI after the developing process is approximately 10 to 100 times that before the developing process, and the hierarchical pattern processing is a powerful tool in realizing high-speed pattern processing when executed at a time before the developing process.
On the other hand, a resizing process is essential to the pattern data processing. When the pattern includes a notch, an oversizing to a predetermined width and an undersizing thereafter for the same predetermined width would eliminate a notch of the predetermined width. In addition, such a resizing process is executed to conform to an interface of a different exposure apparatus and when modifying a design rule.
Conventionally, the designated resizing process is executed by considering only the pattern which is the subject of the resizing process. Thus, when an overlap is generated between the patterns, a merge process is executed to eliminate the overlap. When executing an undersize resizing process, a merge process is executed before the resizing process to prevent a slit from being generated or a slit fill-in process is executed with respect to the slit after the resizing process.
FIG. 1A shows a hierarchical structure of a semiconductor integrated circuit device, and FIG. 1B is a diagram for explaining the layout pattern of the semiconductor integrated circuit device in each level of the hierarchical structure. In FIGS. 1A and 1B, A denotes the structure of an entire semiconductor integrated circuit device (chip), B denotes the structure of a memory cell having several hundred kbits, C denotes the structure of a peripheral circuit, and D denotes the structure of a basic memory cell amounting to several bits.
The data quantity at the time when actually executing the exposure is extremely large. For this reason, exposure data is conventionally made for one 128 kbit memory cell B shown in FIG. 1B, one 128 kbit memory cell B which is formed symmetrically with respect thereto and one peripheral circuit C, and the arranging process is executed in the exposure apparatus. However, since the exposure files are divided, a slit or an overlap (multiple exposure) may be generated between the files when a resizing process is executed.
The following problems occur when an attempt is made to execute the pattern data processing in the levels of the hierarchical structure according to the conventional method.
When an oversize resizing process is executed on the pattern data which is connected between the levels of the hierarchical structure, an overlap is generated and a multiple exposure occurs at a connection of the levels between the basic memory cells D or between the basic memory cell D and the peripheral circuit C as shown in FIG. 2. On the other hand, when an undersize resizing process is executed on the pattern data, a slit is generated between the levels of the hierarchical structure as shown in FIG. 3.
FIG. 4 shows another example of an overlap generated by an oversize resizing process and a slit generated by an undersize resizing process.
When the overlap exists, the overlap portion swells out, i.e., expands, when a scan is made by a vector scan type electron beam exposure apparatus and the swelled, i.e., expanded, portion may touch an interconnection portion. On the other hand, when the slit exists, a disconnection occurs thereby making it impossible to satisfactorily form an LSI element. That is, the resizing process is executed when executing the pattern data processing, and even when no overlap or slit exists in the design data, the overlap and slit are inevitably generated by an oversize resizing process and an undersize resizing process which are peculiar to the apparatus used to produce the semiconductor integrated circuit device.
In order to eliminate the overlap and the slit, a hierarchical structure developing process must be executed after the resizing process and a process such as the merge process and the slit fill-in process must be executed. However, such processes require an extremely long processing time and an extremely large capacity for storing the developed data.
When an attempt is made to eliminate the overlap by finding the pattern at the connection between two levels, it is necessary to look at the connection between one level and another level in which the present process is executed. But this is an extremely complicated process and impractical. For example, FIG.5 shows an example of the undersize resizing process. In FIG.5, the undersize resizing process can be executed normally at parts P1 and P2 because a portion of the chip A does not connect to a portion of the cell B' at the part P1 and a portion of the cell B' does not connect to a portion of the chip A at the part P2. But the undersize resizing process must be executed so that no slit is generated at a part P3 since a portion of the cell B connects to a portion of the chip A. For the chip A, there is no way of knowing how to treat the pattern at the connection unless all of the memory cells B are arranged and the connecting patterns are found, but this is an extremely complicated and troublesome process. For the memory cell B, the shape of the pattern depends on the location of the memory cell B within the chip A and the pattern at the connection has many possibilities, and it is impossible to manage all the data.